The invention relates generally to computer memory architecture. In particular, the invention relates to a memory chip for use in a hierarchical memory system for a computer.
In a computer system, the performance of the memory subsystem is a function of the capacity of the memory and the rate at which data can be read from or written into the memory. The larger and faster the memory is built, the higher performance level one can judge the computer to operate at. However, those computer applications with high performance requirements usually have cost and physical constraints which limit the use of very fast memory chips as the exclusive memory elements for the memory subsystem. These high performance applications usually resort to a hierarchical memory architecture which combines a small but very high speed buffer memory with a more dense but slower memory. The result is a high performance product built at a reasonable price.
One example of a memory system 10 is illustrated in block diagram form in FIG. 1. A single communication path 12 links the memory system 10 to the processor of the computer. The communication path 14 can be either a single serial line or can be a multi-line bus. Within the memory system 10, the communication path is connected to a memory buffer 14 which serves as intermediate storage. Also connected to the buffer 14 is an internal memory bus 16 linking the buffer 14 to a back store array 18. The back store array 18 is very much larger than the buffer 14 but the array 18 typically operates much more slowly than the data rate on the communication path 12 to the processor. The use of the buffer 14 decouples the operating rates of the back store array 18 from that of the communication path 12, thereby allowing the use of large but relatively slow and relatively inexpensive memory chips in the back store array 18. What is thus illustrated in FIG. 1 is a hierarchical memory system with two levels of memories 14 and 18 plus the lower level associated with the user. Memory systems have been proposed in which the hierarchical memory has been extended beyond the illustrated two levels.
The buffer 14 can be an input/output buffer which simply accommodates the differing operating rates of the communication path 12 and of the internal memory bus 16. However, the buffer 14 can be provided with additional functions to perform as a cache memory. In a cache memory, large blocks of data are down-loaded from the back store array 18 to the cache buffer 14. Thereafter, whenever the processor requires data from the block of data already in the cache buffer 14, whether it be a read or a write operation, the access is made directly to the cache buffer 14 without the requirement of an access to the back store array 18. Eventually, any updated data in the cache buffer 14 needs to be up-loaded to the back store array 18 when the cache buffer 14 is required for a different block of data.
The design of the intermediate memory or buffer 14 is crucial to the overall performance of the memory system since it controls the flow of data between the back store array 18 and the processor. The buffer 14 illustrated in FIG. 1 is a two-port buffer because it receives and sends data on two sets of lines 12 and 16. A dual ported memory is described by Lavalee et al in a patent application, Ser. No. 405,812, filed Aug. 6, 1982 now U.S. Pat. No. 4,489,381, and incorporated herein by reference. The memory of Lavalee et al is an array of individually addressable words. As a result, the memory of Lavallee et al can function as an intermediate cache memory. The memory of Lavalee et al has two ports, each connected to their respective parallel busses. Such a port will be called a parallel port. Lavalee et al further provides a buffer at the port to the next higher memory level, for example, the port of the buffer 14 to the back store array 18. Their intermediate memory array is therefore operating at the data rate of the communication path 12 while their buffer can be accommodating the slower flow of data on the internal memory bus 16. One of the disadvantages of the memory of Lavalee et al is the requirement that the fairly large memory array be operating at the rate of the communication path 12 to the processor, that is, that it be operating at processor speeds.
Some computer systems have been proposed in which the communication path 12 is a serial line, that is, a single line rather than a bus, that is operating at very high data rates. The internal memory bus 16 to the back store array 18 would preferably be a fairly wide bus in order to match the data rate, rather than the bit rate, of the back store array 18 to the data rate on the serial communication path 12. It is not believed that the dual ported array of Lavallee et al is applicable to such a system. Furthermore, such a buffer 14 with serial data on one side and parallel data on the other presents several design difficulties if the buffer 14 is to be used as cache memory. Such a cache buffer should easily pass data through from the serial communication path 12 onto the internal memory bus 16. It should also have the capability of quickly replacing portions of its data from the back store array 18 when the serial communication path 12 request access to a piece of data not currently stored in the cache buffer 14. Lastly, the operations to the serial communication path 12 and to the parallel internal memory bus 16 should be made as independent as possible and to operate concurrently in order to speed the overall data transfer.
Haynes discloses in U.S. Pat. No. 3,166,739 a memory array that can be read either serially or in parallel. However this memory does not offer the broad concurrency of operation that is desired. Rao in U.S. Pat. No. 4,347,587 discloses another memory array with both serial and parallel access. However, this duality of access extends only to reading and not to writing operations, which are necessarily serial writing operations, which are necessarily serial writing operations. Furthermore, this duality is accomplished by separate parallel and serial arrays. Fuhrman in U.S. Pat. No. 4,120,048 discusses concurrent random and sequential access operations. However all of his ports are of equal width and the seriality and randomness refers to the address sequence rather than the format of data words. Also, Correlle et al. discloses in U.S. Pat. No. 3,332,066 both single bit and multi-bit access to a core memory, such as would be used for a scratch pad memory. Aichelmann and Neves in U.S. Pat. No. 4,388,701 disclose a multi-layer memory array. However, their ports are all serial. Finally, Stringa in U.S. Pat. No. 4,163,281 disclose a matrix rotator which has the effect of outputting serially a row of data that was inputted in parallel and vice versa for the columns.